Meeting date: 04 apr 2006
Members (asterisk for those attending):
*Arpad Murayni,
*Bob Ross,
*Todd Westerhoff,
*Mike LaBonte,
Paul Fernando,
Barry Katz,
Walter Katz,
Ken Willis,
*Ian Dodd
Lance Wang
*Richard Ward

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Review of ARs:

Mike finish documentation examples.
- in progress

Mike find downloadable SPICE model and measure I/T
- done, will be sent out once HSPICE license problem is resolved

Lance send PCI-X macromodel
- done

Walter test PCI-X macromodel in HSPICE and/or ISPICE
- no report

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Richard Ward from TI:
- Looking into modeling at the next level
- Using Matlab
- Interoperability, SerDes, etc.
- Contacting Mentor and Cadence
- Model performance in HSPICE is a problem
- Has produced AMS models for specific models
- Using Verilog-A
- Has seen Arpad's macro presentation

Where we stand
- Element library
  - Need current buffer element in library
  - Add break statement to avoid convergence problems
- Template library
  - Need more
- Tools
- Testing

Can TI provide designs to macro-model?
- Two halves of a SerDes link
  - Receiver must measure after clock recovery
  - Many receiver parameters - how to model?
- Have HSPICE Si models, rough Verilog behavioral
  - AMS design by Syed Huq
- Thinking of making vendor-specific models
- May have NDA problems, or may have to change models
  - Protection may be required even for macro-models
  - Model structure might be public, but parameters
    would be provided under NDA
- Macro library may not be sufficient
- Could give a presentation on a simplified design
- Accused of using only 5% of library
  - Need to use restricted subset even for digital

AR: Richard prepare short presentation on TI design

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Next meeting: Tuesday 11 apr 2006 12:00pm PT